Ethan Frink — Portfolio

Education

Arizona State University — Tempe

B.S. Computer Science, Cum Laude — Barrett Honors College (May 2025)
M.S. Computer Science, Thesis Track (Expected May 2026), GPA: 4.0
Research focus on computer networks, distributed systems, and performance, with hands-on work spanning networking stacks, operating systems, and reconfigurable hardware.
Core coursework includes Data Structures & Algorithms, Operating Systems, Computer Networking, Databases, Machine Learning, Software Engineering, and Information Assurance.

Research at the intersection of high-performance networking, FPGA acceleration, and system reliability.

Co-authored a research paper on accelerating error detection in network cores using reconfigurable computing (pending acceptance).
Designed FPGA-based redundancy and change-detection pipelines that achieved 4.5× throughput improvements over optimized software baselines.
Built reproducible experimental pipelines to evaluate performance, latency, and scalability trade-offs in hardware-accelerated network systems.
Presented research at workshops and conferences and collaborated regularly with researchers across multiple institutions.

Systems-oriented projects spanning networking, hardware acceleration, and full-stack development.

Designed and implemented network-attached FPGA pipelines using Xilinx Vitis HLS and high-bandwidth memory to accelerate cyclic redundancy check (CRC) and change-detection workloads.
Optimized data movement and memory layouts on Alveo accelerator cards, increasing CRC throughput from ~200 Mbps to over 1 Gbps.
Developed an iOS sports streaming application with live scores and broadcasts, contributing to backend APIs, client-server communication, and security considerations.
Built interactive data visualizations and system dashboards to explore performance metrics and experimental results.

Research and teaching roles focused on performance engineering, low-level systems understanding, and reliability.

Networks Research Intern — RTX BBN Technologies (DARPA QuANET): designed and evaluated FPGA-accelerated change-detection schemes for next-generation secure networking.
Worked closely with senior researchers and government stakeholders, translating research goals into working hardware prototypes and evaluations.
Teaching Assistant — Programming Languages & Compilers: led recitations and office hours focused on C/C++ memory behavior, compiler internals, and advanced debugging techniques.
Guided students through complex projects involving low-level reasoning, GDB-based debugging, and performance analysis.